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Proliferation of power electronics and distributed energy resources (DERs) into the electrical power system (EPS) enables improvements to the network’s resilience against sudden-inception short circuit electrical faults through redundant electrical pathways in meshed configurations and multiple possible distributed generation locations. However, successful operation of fault detection, isolation, and recovery in islanded mode is challenging as protection coordination must include not only the distribution equipment, but also the DERs. Assessment of resilience for candidate EPS architectures against short circuit faults must be performed to understand the trade-offs between network resilience and complexity. This paper proposes a design process, which can be used towards assessing microgrid resilience, by coordinating protection and ride-through settings to maximize the recoverability of a meshed islanded AC microgrid. The design process is demonstrated through a case-study. 

Real-time (RT) simulation of power and energy conversion systems allows engineers to interface both simulation- and hardware-based controls using controller hardware-in-the-loop (CHiL) simulation of networks of power electronic converters (PECs) in order to de-risk highly developmental systems such as next generation electrified transportation systems and dc microgrids. CHiL exploration and performance verification moves a design from Technology Readiness Level (TRL) 3 to TRL 4 without incurring significant cost investments in developmental hardware platforms, which otherwise discourages such endeavors. A real-time CHiL simulation platform suitable for explorations of protective equipment, protection schemes and networked PEC dc and mixed dc-ac power distribution architectures must be capable of simulating common-mode behavior, various grounding schemes, and fault transients at sufficiently high resolution. This paper demonstrates this capability using a Latency-Based Linear Multistep Compound (LB-LMC) simulation method implemented in a commercially sustainable, adaptable and expandable FPGA-based test and instrumentation platform. The proposed CHiL platform achieves real-time power system simulations, including detailed switching commutations of networked PECs, with 50 ns resolution, and faithfully produces resonant and transient behaviors associated with line-to-ground (LG) and line-to-line (LL) faults and fault recovery in ungrounded PEC-based dc systems. This resolution in RT cannot be achieved with today’s commercial off-the-shelf CHiL platforms. This paper demonstrates the need for high resolution RT simulation of LG and LL faults within dc systems, and demonstrates a CHiL approach that enables dc protection design explorations and protective control hardware testing while taking into account the realistic aspects that affect fault characteristics in PEC-based dc systems, such as cable current rating and length, cable and PEC parasitic LG capacitance and PEC i... 

Real Time (RT) simulation of Power Electronics (PE) allows engineers to interface real-time controls for controller hardware-in-the-loop CHiL. CHiL verification moves a design from Technology Readiness Level (TRL) 3 to TRL 4. For RT CHiL simulation of DC protection systems, the RT simulation platform must be able to simulate common mode behavior, various grounding schemes, and fault transients at sufficiently high resolution so as not to interfere with the protection system design. This paper demonstrates this capability using a Latency Based Linear Multistep Compount (LB-LMC) simulation method implemented in Field Programmable Gate Arrays (FPGAs), in order to achieve 50ns resolution of common mode behaviors, including Line-to-Ground (LG) overvoltages resulting from LG faults and fault recovery in ungrounded DC systems. This resolution in RT cannot be achieved with today's commercial off-the-shelf (COTS) RT CHiL platforms. Furthermore, this capability can be expanded to other grounding schemes and larger PE networks, enabling RT CHiL validation of protection schemes for networks of power electronic converters at TRL 4.